1. Field of the Invention
The present invention relates generally to a data receiver, and more particularly, but not by way of limitation, to a data receiver of a semiconductor device.
This application claims the benefit of Korean Patent Application No. 10-2006-0100513, filed on Oct. 16, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
The data transmission speed between semiconductor chips has increased. However, in the improvement of system performance, the increase of the data transmission speed is restricted due to the physical limit of a channel. A transmission line on a printed circuit board (PCB) has a feature of a low pass filter. Accordingly, when a data signal is transmitted at a speed of several gigabits per second (Gb/s), a gain of the transmitted data signal through the transmission line decreases, and inter symbol interference (ISI) of the transmitted data signal is generated.
Also, the ISI is generated by a reflection wave due to the discontinuation of impedance on the channel. In particular, the ISI becomes more severe on a dynamic random access memory (DRAM). This is because the signal transmission method of the DRAM is a single ended signaling method and the ISI may increase due to a multi load and a connector.
An equalizer may be used to remove the ISI. The equalizer includes a pre-conditioner at a transmission end, a linear equalizer at a receiving end, and a decision feedback equalizer (DFE). In particular, the DFE is widely used because it does not amplify a high frequency noise. A DFE receiver of a DRAM using the DFE method removes the ISI from the currently received signal based on a previously input data value. The DFE receiver can be embodied in many ways and, as an example, there is a method in which the ISI is removed by changing a reference voltage of a receiver.
FIG. 1 is a circuit diagram of a single tap DFE receiver for removing ISI by changing a first reference voltage VR of a receiver 10. Referring to FIG. 1, the receiver 10 includes an amplifier 20, a latch 30, a tap 40, and an adder 50. The amplifier 20 receives a first data signal DQ and outputs a second data signal DQ′ based on the input first data signal DQ and the first reference voltage VR. The latch 30 latches the second data signal DQ′ in response to a clock signal CLK. A coefficient Cf of the tap 40 is updated based on the second data signal DQ′ latched in the latch 30. The adder 50 is added the updated coefficient Cf of the tap 40 and a second reference voltage Vref. The output of the adder 50 is the first reference voltage VR.
FIG. 2 is a conceptual view for explaining the operation of the single tap DFE receiver 10 of FIG. 1. Referring to FIG. 2, the input data DQ (for example, the first data signal of FIG. 1) is sampled at predetermined sampling times S1 through S7 in response to the clock signal CLK. When a value of the data DQ input in a previous sampling time (for example, the data sampled at time S3) is in a low level, gain of the present data DQ, (for example, the data sampled at time S4) may be decreased due to the ISI. In this case, the tap 40 determines the coefficient Cf (=−C1) based on the data value input at the previous sampling time. For example, the data value sampled at time S3 is in a low level (DQ=low). The adder 50 adds the determined coefficient −C1 of the tap 40 and the second reference voltage Vref.
The amplifier 20 determines the present data value based on a result of comparison between the output VR (=Vref−C1) of the adder 50 and a value of the present data DQ (i.e., the data value sampled at time S4). Also, the coefficient Cf (=+C1) of the tap 40 is determined based on the data value of the input data DQ at a previous sampling time, for example, the data value sampled at time S1 (DQ=high). Thus, the first reference voltage VR=Vref+C1. Accordingly, the single tap DFE receiver 10 removes noise due to the ISI during the determination of the present data by controlling the reference voltage VR based on an input data value at a previous sampling time.
However, in the single tap DFE receiver 10, the feedback loop that includes tap 40 causes delay. The maximum operation speed of a semiconductor device (for example a DRAM) is thus limited. To address the above problem, a loop unrolling DFE method may be used for the receiver.
The loop unrolling DFE method is an unrolling method for reducing the feedback delay. In the loop unrolling DFE method, two comparison blocks are used to make two decisions for each data cycle, and one of the two decisions is selected as a final data output value based on the data value determined in a previous cycle.
FIG. 3 is a circuit diagram of a conventional loop unrolling DFE receiver 300. Referring to FIG. 3, the loop unrolling DFE receiver 300 uses a four interleaved method for determining input data DQ based on four clock signals CLK0, CLK90, CLK180, and CLK270, each clock having a phase difference of about 360°/4, that is, 90°. The receiver 300 includes a first equalizer DFE1, a second equalizer DFE2, a third equalizer DFE3, and a fourth equalizer DFE4. Each of the first through fourth equalizers DFE1-DFE4 has the same structure except for input and output signals.
The first through fourth equalizers DFE1-DFE4 determine data values DV1, DV2, DV3, or DV4 of the input data DQ based on the respective first through fourth clock signals CLK0, CLK90, CLK180, and CLK270, each of the clocks having a different phase. For example, the clock signals CLK90, CLK180, and CLK270 of the second through fourth equalizers DFE2, DFE3, and DFE4 have phase differences of 90°, 180°, and 270° compared to the phase of the clock signal CLK0 of the first equalizer DFE1. As a result, each of the equalizers DFE1 through DFE4 sequentially determines the input data DQ based on each of the clock signals CLK0 through CLK270, respectively, and outputs determined data values DV1 through DV4.
Equalizer DFE1 includes a first SAFF (sense amplifier-based flip flop) 310, a second SAFF 320, a multiplexer (MUX) 330, and a third SAFF 340. The first SAFF 310 includes a first differential amplifier 312 and a first latch 314. The first differential amplifier 312 differentially amplifies the difference between the input data DQ and the first voltage VH (a high level voltage), based on the first clock signal CLK0. The first latch 314 latches the output of the first differential amplifier 312.
The second SAFF 320 includes a second differential amplifier 322 and a second latch 324. The second differential amplifier 322 differentially amplifies the difference between the input data DQ and the second voltage VL (a low level voltage) based on the first clock signal CLK0. The second latch 324 latches the output of the second differential amplifier 322.
The multiplexer 330 outputs one of the outputs of the first latch 314 and the second latch 324 based on the value DV4 of the data DQ determined by the fourth equalizer DFE4.
The third SAFF 340 detects the output of the multiplexer 330, amplifies the detected signal, and outputs the amplified signal as a determined data value DV1 based on the first clock signal CLK0. Thus, the data value DV1 output by the first equalizer DFE1 is determined in part by the data value DV4 output by the fourth equalizer DFE4 in a previous cycle. For example, when the value of the data DQ determined by the fourth equalizer DFE4 is at a high level, the multiplexer 330 of the first equalizer DFE1 selects the output of the first latch 314. In this instance, the data value DV1 output from the first equalizer DFE1 is then determined based on the result of comparison between the input data DQ and the first reference voltage VH, (a high level voltage).
In contrast, when the value of the data DQ determined by the fourth equalizer DFE4 is at a low level, the multiplexer 330 of the first equalizer DFE1 selects the output of the second latch 324. In this instance, the data value DV1 output from the first equalizer DFE1 is determined based on the result of comparison between the input data DQ and the second reference voltage VL (a low level voltage).
The maximum operation speed of the semiconductor device having the loop unrolling DFE receiver 300 of FIG. 3 is limited by the time consumed by the latches 314 and 324 and the multiplexer 330. Also, since each of the equalizers DFE1 through DFE4 include three SAFFs, a DRAM or other semiconductor using the DFE receiver 300 has large circuit size and high power consumption. Therefore, there is a need to reduce the circuit size and power consumption of the conventional loop unrolling DFE receiver and decrease time delay during the data determination.